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MITSUBISHI ICs (LSI)
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M64403FP
ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
DESCRIPTION
The M64403FP performs the decoding for RS (Reed Solomon) code which primitive polynomial:P (X)=X8+X4+X3+X2+1 and its generation polynomial:G (X)= (X-j). M64403FP can set the code length and check byte length, so it is able to be adopted to various systems.
j=0 d-2
APPLICATION
DVD player, DVD-ROM (DVD:Digital Video Disc), DBS (Direct Broadcasting by Satellite), High density floppy disk, Hard disk, CATV (Cable TV), MD (Mini Disc), DVC (Digital Video Cassette), DAT (Digital Audio Cassette), DCC (DIgital Compact Cassette), DVB (Digital Video Broadcast), CD-DA (Compact Disc-Digital Audio), CD-ROM (Compact Disc-Read Only Memory), other communication systems and storage media etc.
FEATURES
It adopts three stages pipe line operation (Syndrome stage, Euclidean stage, Chen search & error value stage), so it realizes high speed error correction operation. Capable of erasure correcting function and it improves error correction performance. * Where error counts (e), erasure counts () and design distance (d) have followed restriction. 2e + < d Capable of parameter register programing. (1) Four kinds of code parameter which code length and check byte length are programmable. (Good for the product code that has plural code parameters.) * Where, maximum code length (L) are 255 bytes and maximum check byte length (d-1) are 16 bytes. (2) Programmable for erasure threshold. (3) Programmable for four kinds of decoding mode.
PIN CONFIGURATION (TOP VIEW)
58 ORDY 59 OUTR 51 CRDY 50 CRDF 49 CORF 48 TES2 47 ERAF 46 TES7 45 VDDO 44 OMD0 43 OMD1 42 OMD2 41 CLKM 40 VSSO 39 RES 38 VDDO 37 ARM0 36 ARM1 35 ARM2 34 ARM3 33 DAI0 32 DAI1 31 DAI2 56 EROV 68 ENM4 67 ENM3 66 ENM2 65 ENM1 64 ENM0 62 SYCR 63 UNCF 77 DAO7 76 DAO6 75 DAO5 74 DAO4 73 DAO3 72 DAO2 71 DAO1 69 DAO0 60 SBFB 78 ELO0 55 TES3 54 TES1 57 IRDY 79 VDDO 61 VDDO
70 VSSO
53 VSSO
ELO1 ELO2 ELO3 ELO4 ELO5 ELO6 ELO7 VSSO DAM0 DAM1 DAM2 DAM3 DAM4 DAM5 DAM6 DAM7 VDDO OTRG EREN ADDC
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
100
M64403FP
TESTE 20
TESM 21
CLKI 22
VSSO 23
DAI7 24
DAI6 25
DAI5 26
DAI4 27
VSSI 28
VDDI 29
52 VDDI
80 VSSI
READ 10
CSEL 11
PWDN 12
REST 13
DHEF 14
CLKO 15
DOEN 17
CLKE 18
NOEN 3
MOD2 6
MOD1 7
MOD0 8
WRTE 9
Outline 100P6S-C
ERMF 19
VDDO 2
LOEN 4
DIEN 5
DAI3 30
VSSO 1
RES 16
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M64403FP
ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
BLOCK DIAGRAM
IRDY MOD0 - 2 DIEN DHEF DAI0 - 7 EREN INPUT I/F SYNDROME CIRCUIT
REST CLKI CLKM CLKE CLKO PWDN
ARM0 - 3 MICRO COMPUTER I/F CSEL WRTE READ DAM0 - 7
EUCLIDEAN CIRCUIT
OTRG ADDC OUTR DAO0 - 7 DOEN ELO0 - 7 LOEN ENM0 - 4 NOEN ERMF OMD0 - 2 CRDY ORDY CRDF OUTPUT I/F CHEN SEARCH & ERROR VALUE CIRCUIT CONTROL CIRCUIT
SYCR ERAF TESTE TESM UNCF CORF EROV SBFB
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M64403FP
ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI VO IIK IOK IO IDD ISS Tstg PdOUT Parameter Supply voltage Input voltage Output voltage Input protection diode current Output parasitic diode current Output current VDD supply current VSS supply current Storage temperature Output Output buffer@IOL=4mA load Output buffer@IOL=1mA Ratings Min. Max +6.5 -0.3 -0.3 VDD+0.3 -0.3 VDD+0.3 20 20
IOL=20 IOH=-26
Unit V V V mA mA mA mA mA C
MHz*pF
-55
81 81 150 2200 760
RECOMMENDED OPERATING CONDITION
Symbol VDD Ta VI tr, tf Parameter Supply voltage Operating temperature Input voltage Input rise & fall time Normal input Schmit input Min. 4.75 -20 0 Limits Typ. 5.0 +25 Max. 5.25 +70 VDD 500 5 Unit V C V nsec msec
ELECTRICAL CHARACTERISTICS
Symbol VIL VIH VTVT+ VH VOL VOH IOL Output current IOH IIL IIH IOZL IOZH RD CI CO CIO IDD Input current Output leak current Pull down resistance Input terminal capacitance Output terminal capacitance I/O terminal capacitance Supply current VDD=4.5V, VOH=4.1V VDD5=5.5V, VDD5=5.5V, VDD5=5.5V, VDD5=5.5V, VDD5=5.0V, VI=0V VI=5.5V VI=0V VI=5.5V VI=5.0V -1 -1 -1 -1 3 7 7 7 Input voltage (TTL interface) Schmitt input voltage (TTL interface) Output voltage Parameter VDD=5.0V VDD=5.0V VDD=5.0V VDD=5.0V, IO <1A VDD=4.5V, VOL=0.4V Test conditions Min. 0 2.2 0.7 1.4 0.3 4.95 4 (1) 1 (2) -4 (3) -1 (4) +1 +1 +1 +1 16 15 15 15 2 Limits Typ. Max. 0.8 5.25 1.35 2.2 1.2 0.05 Unit V V V V V V V mA mA mA mA A A A A k pF pF pF mA
f=1MHz, VDD=0V VDD5=5.0V, VI=5.0V
( 1) : Rating for 4mA output buffer ( 2) : Rating for 1mA output buffer
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M64403FP
ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
MICRO COMPUTER INTERFACE
Parameter register setting method (write) is described as follows. (See page7 about sequence chart : See below diagram about micro computer I/F and register table.) 1. Perform power on reset. 2. Set various parameters (code length-1, check byte length, erasure correction threshold) to below parameter register table. 3. Set decode operation mode parameters to address-E. (See address-E description) See sequence chart page7 (micro computer I/F sequence) as for read from parameter register, see below table as for register table. Parameter register table address (Hex) 0 1 2 3 4 5 6 7 8 9 A B C D E F R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R -- R/W -- Initial (Hex) 00 00 00 00 00 00 00 00 00 00 00 00 -- -- -- -- set data (Hex) FE FE FE FE 10 10 10 10 10 10 10 10 -- -- -- -- description code (0) code length-1 code (1) code length-1 code (2) code length-1 code (3) code length-1 code (0) check byte length code (1) check byte length code (2) check byte length code (3) check byte length code (0) erasure threshold code (1) erasure threshold code (2) erasure threshold code (3) erasure threshold real erasure counts which is derived from syndrome calculation reserve decode operation mode reserve
Address-E description address (Hex) E data D7 D6 D5 D4 D3 D2 D1 D0
means "0" fixed. D0 (bit0) D3 (bit3) 0:constrained error correction mode 0:error value output mode 1:erasure correction priority mode 1:internal correction mode
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M64403FP
ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
DECODE MODE SETTING METHOD
Decode mode is able to set at IRDY=H. Decode mode table is as follows. Decode mode should be changed after all operations that are set before changing. Decode mode table MOD0 0 1 0 1 0 1 0 1 MOD1 0 0 1 1 0 0 1 1 MOD2 0 0 0 0 1 1 1 1 code (0) code (1) code (2) code (3) code (0) code (1) code (2) code (3) mode error correction error correction error correction error correction erasure correction erasure correction erasure correction erasure correction
ERASURE FLAG INPUT METHOD AND ERASURE CORRECTION MODE
Erasure correcting mode is set by the setting of erasure threshold to address 8 to B for parameter register and the setting of MOD2=H for decode mode signal. Erasure flag (EREN) should input H by synchronization with symbol data of code word. Follows are about erasure threshold. (1) Constrained error correction mode is derived when the bit0 (D0) of the parameter register address-E is set to L. If the input erasure count is over the erasure threshold value(3), the operation is adopted ordinary error correction mode by force. (2) Erasure correction priority mode is derived when the bit0 (D0) of the parameter register address-E is set to H. If the error is detected at syndrome calculation and erasure count is over the erasure threshold value(4) M64403FP regards , its operation as uncorrectable and correcting operation doesn't execute. In any cases ((3) ,(4) ), EROV (erasure over flag) changes to H.
CODE WORD INPUT METHOD
Code word is able to input at IRDY=H. IRDY changes H to L when head symbol for code word is input. And IRDY changes L to H when the last symbol of code word is input. DHEF should be H and DIEN should be L when the head symbol of code word is input. DIEN is input enable signal for code word and while it's L, input data is recognized as valid data and latched to the internal circuit at rising edge of CLKI. If the syndrome calculation for the 2nd code word finishes while the 1st code word is executed at Euclidean calculation stage, the syndrome data that is latched internally is overwritten (called syndrome collision) and the correcting operation for the 1st code word is impossible. In this case, SYCR changes to H and informs external of its status. (If the last symbol of code word is input at SBFB=H, decoding is operated safely.) SYCR which changes to H is reset by system reset (REST=L).
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M64403FP
ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
CORRECTED DATA OUTPUT METHOD
When the decode operation finishes and correction result is able to output to a code word, OUTR changes to H for one period for CLKO. In this case, error location data is shown on ELO0 to ELO7, error value is shown on DAO0 to DAO7 and error correction count or erasure count is shown on ENM0 to ENM7. (Details are described later.) When output enable signals (LOEN, DOEN, NOEN) are set to L (active mode), respective data (error location, error value, error or erasure count) are able to output. When these output enable signals are set to H, respective data bus change to high impedance status. Error location data (ELO0 to ELO7) 00 hex means the location of head data for input code word. Error value data (DAO0 to DAO7) corresponds with error location data (ELO0 to ELO7). ADDC should be L for one period of CLKO in order to output next error location and next error value. (See page10 : Correction data operation sequence chart) ENM0 to ENM4 outputs error correcting count at ERMF=L, erasure count at ERMF=H. This erasure count means real error count at constrained error correction mode, total count for real error and erasure at erasure correction priority mode. And this erasure count includes empty erasure (it means error value is zero). If erasure count excesses 31 dec, ENM0 to ENM4 shows 31 dec. After the external circuit read error count/error location/error value for a code word, OTRG should change L to H only one time by synchronization with CLKO clock. Data shift for internal pipe line circuit is executed by this operation. If this operation is so late, registers in the internal pipe line become full. And data collision may occur if code word is input more and its syndrome data is generated. In this case, M64403FP informs external of its status and SYCR changes to H. (If the last symbol of code word is input at SBFB=H, decoding is operated safely.) SYCR which changes to H is reset by system reset (REST=L).
OUTPUT CONTROL SIGNAL
When OUTR changes to H, CORF (error detected flag), UNCF (uncorrectable flag) and EROV (erasure over flag) are output. CORF changes to L when M64403FP regards input code word as no error. CORF changes to H when M64403FP detects error. UNCF changes to H when M64403FP regards the error correction as impossible. If the input erasure flag count excesses erasure threshold value with erasure correction priority mode, UNCF changes to H also. OMD0 to OMD2 show the current operated code word's decode mode which was set by MOD0 to MOD2.
INTERNALCORRECTION MODE
The internal correction mode is active when the bit3 (D3) of parameter register address-E is set to H. In this internal correction mode, the code word that was input already and shown by OMD0 to OMD2 input to ELO0 to ELO7. In order to recognize the header symbol of input data, OTRG should be H by synchronization with the header symbol of code word. ADDC should be L while valid code word is input. Corrected data is output from DAO0 to DAO7 after three clocks delay. OUTR changes to H by synchronization with header symbol in order to show the header symbol of corrected code word. CRDY changes to L by synchronization with output code word. CRDF changes to H for corrected portion. In addition, ORDY changes to H while output period of information symbol in order to distinguish from code word from information symbol and check symbol.
MISOPERATION FOR ODD CHECK BYTE NUMBER
M64403FP have no good operation when check byte number are just d/2 (d=check byte number+1) as UNCF don't to change to H, and misdata is output. But we can judge the misoperation when ENM<4:0> indicates d/2 in error correction mode, and ENM<4:0> indicates d/2 when erasure number=0 or EROV=H in erasure correction mode.
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M64403FP
ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
ERROR CORRECTION TIME
M64403FP is able to perform consecutive error correction operation by bellowed three stage pipeline architecture. * 1st stage...............Syndrome calculation (operation step:A1=code length+20) * 2nd stage............. Euclidean calculation (operation step:A2=See table.2) * 3rd stage.............. Chen search & error value calculation (operation step:A1=code length+20) Table. 1 1st code 2nd code 3rd code 4th code pipe1 1st stage pipe2 2nd stage 1st stage pipe3 3rd stage 2nd stage 1st stage pipe4 correction 3rd stage 2nd stage 1st stage pipe5 correction 3rd stage 2nd stage pipe6 pipe7
correction 3rd stage
correction
Table. 1 shows the operation flow in pipe line. As for the 1st code, M64403FP output error correction data at pipe4 after 1st stage is operated at pipe1, 2nd stage is operated at pipe2 and 3rd stage is operated at pipe3. Therefore, the error correction has a latency of three stages. The maximum step count for each pipe means the maximum steps among above mentioned 1st stage to 3rd stage. Where, the design distance decides the step count at the 2nd stage. (See Table. 2) Table. 2 Design distance Euclidean calculation steps (erasure correction) Euclidean calculation steps (error correction) 17 330 290 16 290 270 15 260 250 14 230 220 13 210 190
(Ex.1) In the case of code length=100, design distance=11 A1=100+20=120, A2=160 A2>A1 So maximum operation step for one pipe is 160. Therefore, correction data is obtained 480 steps (160 x 3) later from the input of 1st code word.
12 190 180
11 160 150
10 140 140
9 120 110
8 110 100
7 90 80
6 80 80
5 70 60
4 60 60
3 50 40
2 30 30
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M64403FP
ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
CORRECTING OPERATION STEPS IN PIPE LINE
(Ex.1) code length=182, design distance=11 CLKI=CLKE=CLKO=25MHz error correction (no erasure)
202clk=8.08s
202clk=8.08s
202clk=8.08s
202clk=8.08s
202clk=8.08s
202clk=8.08s
1st code word
code word input 1st stage operation
2nd stage operation
3rd stage operation
correction data access period
2nd code word
code word input 1st stage operation
2nd stage operation
3rd stage operation
correction data access period
3rd code word
code word input 1st stage operation
2nd stage operation
3rd stage operation
correction data access period
Correction data is obtained three stages later (In this case, 2023=606clk 24.24s) by input of consecutive code words.
(Ex.2) code length=208, design distance=17 CLKI=CLKE=CLKO=25MHz erasure correction
290clk=11.6s
290clk=11.6s
290clk=11.6s
290clk=11.6s
290clk=11.6s
290clk=11.6s
1st code word
code word input 1st stage operation
2nd stage operation
3rd stage operation
correction data access period
2nd code word
code word input 1st stage operation
2nd stage operation
3rd stage operation
correction data access period
3rd code word
code word input 1st stage operation
2nd stage operation
3rd stage operation
correction data access period
Correction data is obtained three stages later (In this case, 2903=870clk 34.8s) by input of consecutive code words.
MICRO COMPUTER I/F R/W SEQUENCE CHART
Note. READ=0 and WRTE=0 is inhibited at same time
address
ARM [3:0]
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CSEL
WRTE
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1
READ
DMI [7:0]
data
address
ARM [3:0]
CSEL
1
WRTE
READ
DMO [7:0]
data
address #1 address #2
ARM [3:0]
CSEL
1
WRTE
READ
MITSUBISHI ICs (LSI)
M64403FP
ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
DMO [7:0]
data #1
data #2
CORRECTING DATA OPERATION SEQUENCE CHART
(Where necessary parameter is set already.)
CLKI CLKO
REST
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IRDY
Syndrome calculation is enable@IRDY=1:under calculation=0 Change to 1 after whole code word is input.
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MOD [2:0]
DHEF=1, DIEN=0 are onlyheader symbol for code word.
DIEN
DHEF
DAI [7:0] D3 D4 D181 D0 D5
D0
D1
D2
D1
D2
D3
D4
OTRG
Correcting data read finish (Renewal trigger to next step) Correction data renewal enable Correction data output ready
ADDC
OUTR
DAO [7:0] L0 L1
XX
P0
P1
P2 L2
XX XX
ELO [7:0]
XX
ENM [4:0]
0
03
ERASURE COUNT=00
03
OMD [2:0]
ERMF
UNCF
MITSUBISHI ICs (LSI)
M64403FP
ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
CORF
1
EROV
CONSECUTIVE DECODE SEQUENCE CHART (1)
(Only one kind of code exists)
REST
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IRDY
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DAI [7:0] 3 WORD0 4 WORD0 5 WORD0 6 WORD0
1 WORD0
2 WORD0
7 WORD0
DHEF
DAO [7:0]
1
2
3
4
5
ELO [7:0]
1
2
3
4
5
OUTR
OTRG
ADDC
UNCF correcting status no error status uncorrectable status
CORF
EROV
ERMF 0
MITSUBISHI ICs (LSI)
M64403FP
ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
ENM [4:0]
1
2
3
4
5
Note. DAO and LOE output first error value/location @ OUTR=H. After all of error value/location for error count are output, they output zero. Error value/location output zero at no error and uncorrectable state.
CONSECTIVE DECODE SEQUENCE CHART (2)
(Ex : Two kinds of code parameter exist (Product code))
1
REST
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IRDY
DAI [7:0] 11 WORD n n code 12 WORD n 13 WORD n
9 WORD m
10 WORD m
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m code
MOD [2:0] decoding operation mode for n code
decoding operation mode for m code
DAO [7:0] 8 10 9
11
ELO [7:0] 8 10
9
11
OUTR
OTRG
ADDC
UNCF
CORF
EROV
ERMF
0 8 9 10 11
ENM [4:0]
OMD [2:0]
decoding operation mode for m code decoding operation mode for n code
MITSUBISHI ICs (LSI)
M64403FP
ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
Note. DAO and LOE output first error value/location @ OUTR=H. After all of error value/location for error count are output, they output zero. Error value/location output zero at no error and uncorrectable state.
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ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
EXAMPLE FLOW CHART FOR GENERAL PRODUCT CODE DECODING
In the case of C1C2C1 repeat correction as a decoding method
START
PWDN=0 Yes PWDN=1
No
REST=LH
Set decoding mode parameter register address-E. (Example) Set C1's error corection mode for code (0) and C2's erasure correction mode for code (1) -Example for product code constitutionCode word for C1 direction Code word C2 direction
Set necessary data to the parameter register address 0 to B
1
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ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
1
Set decoding mode Set MOD [0:2] for C1 (1st time)
Set decoding mode Set MOD [0:2] to C2
Recognition of header symbol for code word DHEF=1?
No
Recognition of header symbol for code word DHEF=1?
No
Yes
Yes
C2decode C1 (1) decode
C1 (1) decode finish? Yes
No
C2 decode finish? Yes Set decoding mode Set MOD [0:2] to C1 (2nd time)
No
Recognition of header symbol for code word DHEF=1?
No
Yes
C1 (2) decode
C1 (2) decode finish? Yes 1
No
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ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
INPUT TIMING
tc (CLKI) tw (CLKI) CLKI DAI<7:0> EREN DIEN MOD<2:0> DHEF TESTE tsu (CLKI) th (CLKI)
Symbol tc (CLKI) tw (CLKI) tsu (CLKI) th (CLKI) CLKI CLKI CLKI CLKI
Parameter clock period clock pulse width setup time hold time
Limits (Min.) 40 16 5 10
Unit ns ns ns ns
tc (CLKO) tw (CLKO) CLKO
Symbol tc (CLKO) tw (CLKO) tsu (CLKO) th (CLKO)
tsu (CLKO) th (CLKO)
Parameter CLKO CLKO CLKO CLKO clock period clock pulse width setup time hold time
OTRG ADDC ELO<7:0>
Limits (Min.) 40 16 5 10
Unit ns ns ns ns
tcw
ARM<3:0> tsu (A) CSEL tw (W) WRTE tsu (C) trec (W)
Symbol tcw tsu (A) tsu (C) trec (W) tw (W) tsu (D) th (D)
Parameter Write cycle time Address setup time Chip select setup time Write recovery time Write ulse width Data setup time data hold time
Limits (Min.) 40 10 10 10 10 5 10
Unit ns ns ns ns ns ns ns
DAM<7:0>
tsu (D)
th (D)
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ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
OUTPUT TIMING
At output load capacity=50pF
CLKO ENM<4:0> DAO<7:0> ELO<7:0> UNCF CORF OUTR OMD<2:0>
Symbol td (CKO)
Parameter CLKO output propagation time
Limits (Max.) 20
Unit ns
td (CKO)
CLKI
Symbol td (CKI)
Parameter CLKI output propagation time
Limits (Max.) 20
Unit ns
SYCR
td (CKI)
NOEN DOEN LOEN
Symbol ta (OE) tdis (OE)
Parameter Output enable time Output disable time
ENM<4:0> DAO<7:0> ELO<7:0> ta (OE) tdis (OE)
Limits (Max.) 15 15
Unit ns ns
tcr
ARM<3:0> ta (A) ta (C) CSEL tdis (C)
ta (R) READ tdis (R)
Symbol tcr ta (A) ta (C) ta (R) tdis (C) tdis (R)
Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable access time (from CSEL) Output disable access time (from READ)
Limits
40 (min) 10 (max) 10 (max) 10 (max) 10 (max) 10 (max)
Unit ns ns ns ns ns ns
DAM<7:0>
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ERROR CORRECTION WITH VARIABLE LENGTH AND DISTANCE
DESCRIPTION OF PIN
Pin No. 1, 23, 40, 53, 70, 88 2, 38, 45, 61, 79, 97 16, 39 28, 80 29, 52 3 4 5 6 to 8 9 10 11 12 13 14 15 17 18 19 20 21 22 24 to 27 30 to 33 34 to 37 41 42 to 44 46 47 48 49 50 51 54 55 56 57 58 59 60 62 63 64 to 68
69, 71 to 77 78, 81 to 87
Name VSSO VDDO RES VSSI VDDI NOEN LOEN DIEN
MOD2 to MOD0
I/O -- -- -- -- -- I I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O O O O O O I/O I/O I I I
I/O structure -- -- -- -- -- TTL input TTL input TTL input TTL input TTL schmitt trigger input TTL schmitt trigger input TTL schmitt trigger input TTL schmitt trigger input TTL schmitt trigger input TTL input TTL schmitt trigger input TTL input TTL input TTL input TTL input TTL input TTL schmitt trigger input TTL input TTL input TTL output (4mA) TTL output (4mA) TTL output (1mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL output (4mA) TTL3 state output (4mA) TTL3 state output (4mA) TTL I/O (Pull down Rd=2k) TTL I/O (Pull down Rd=2k) TTL input TTL output (4mA) TTL input
I/O type
Description of function GND for output +5V for output reserve GND for input +5V for input output enable for ENM0 to 4 0:Enable 1:HiZ output enable for ELO0 to 7 0:Enable 1:HiZ Symbol data input enable 0:Enable decoding mode setting MOD2:MSB MOD0:LSB micro computer I/F write enable 0:Enable micro computer I/F read enable 0:Enable micro computer I/F chip select 0:Select power save 0:power save system reset 0:Reset symbol data header 1:Data head data output clock (Typ.13.5MHz) output enable for DAO0 to 7 0:Enable 1:HiZ internal operation clock (Typ.13.5MHz) output enable for ENM0 to 7 1:erasure counts 0:correcting counts test mode selection 0:decoding 1:testing test mode selection 0:decoding 1:testing symbol data input clock (Typ.13.5MHz) symbol data input bus DAI7:MSB DAI0:LSB micro computer I/F address bus ARM3:MSB ARM0:LSB CLKI monitor (Typ.13.5MHz) decoded operation mode (relative to MOD0 to 2) test monitor output erasure flag output 1:Enable test monitor output error detection flag 0:No Error 1:detected correction flag 1:corrected data output valid flag 0:valid test monitor output test monitor output erasure over flag 1:over symbol data input ready 1:Ready data flag 0:data output ready 1:Ready/output data header (@ internal correction mode) 1:header syndrome data collision prevention signal syndrome data collision alarm 1:alarm (collision) uncorrectable flag 1:Uncorrect
error correction counts/erasure counts output bus ENM4:MSB ENM0:LSB
-- -- -- -- -- T22N T22N T22N T22N U22N U22N U22N U22N U22N T22N U22N T22N T22N T22N T22N T22N U22N T22N T22N O65T O65T O63T O65T O65T O65T O65T O65T O65T O65T O65T O65T O65T O65T O65T O65T O65T Z65T Z65T TH2N TH2N T22N O65T T22N
WRTE READ CSEL PWDN REST DHEF CLKO DOEN CLKE ERMF TESTE TESM CLKI
DAI7 to DAI4 DAI3 to DAI0 ARM3 to ARM0
CLKM
OMD2 to OMD0
TES7 ERAF TES2 CORF CRDF CRDY TES1 TES3 EROV IRDY ORDY OUTR SBFB SYCR UNCF
ENM0 to ENM4 DAO0 to DAO7 ELO0 to ELO7 DAM0 to DAM7
error value output bus DAO7:MSB DAO0:LSB data input (for correction) /error location output bus ELO7:MSB ELO0:LSB micro computer I/F bus DAM7:MSB DAM0:LSB renewal trigger 01:renewal/input data (@internal correction mode) 1:header erasure flag input 1:@erasure input output data renewal 0:Next/code word valid (@internal correction mode) 0:valid
89 to 96 98 99 100
OTRG EREN ADDC

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